Yulong Aquila II

Full FPGA digital signal low jitter processing module, YULONG JIC (fitter and Interfacing Control)

YULONG JIC digital signal reception, low noise clock synchronization FIFO buffer, 2 level PLL phase locked loop

ESS9038PRO dual decoding mode synchronous mode, asynchronous mode freely switch, two completely different sounds

PCM 768 KHz, DSD 512 fully balanced low impedance output decoding

Analog volume control, high current drive pre-amplifier

Analog volume control, optimized low-impedance headphones, fully balanced headphone amplifier

Double-loop cattle multi-group multi-stage linear power supply

New IOS, Android mobile phone, tablet optimization, easy, simple and good sound

IPS wide viewing angle display up to 99-level precision analog volume adjustment, suitable for headphones with different impedance

The one-piece non-splicing aluminum alloy shell metal tiger claw shock absorber has beautiful and generous feet, strong and practical

FPGA digital signal reception and demodulation SPDIF / 0ptical / AES support DoP64, DoP128 PCM 384KHz

USB supports DoP64, DoP128, Native DSD64 128, 256, 512, PCM 16-32bit, 32-768KHz

Support Windows. MAC OS IOS, Android, Linux and other operating systems